Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
214
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
17.8.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x5
Reset:
0x00
Property:
Write-Protected
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – EW: Early Warning Interrupt Enable
0: The Early Warning interrupt is disabled.
1: The Early Warning interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the Early Warning interrupt.
0: The Early Warning interrupt is disabled.
1: The Early Warning interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the Early Warning interrupt.
Bit
7
6
5
4
3
2
1
0
EW
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0