Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
246
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
18.8.14 Interrupt Flag Status and Clear - MODE0
Name:
INTFLAG
Offset:
0x08
Reset:
0x00
Property:
-
z
Bit 7 – OVF: Overflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will
be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will
be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
z
Bit 6 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTEN-
CLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTEN-
CLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
z
Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – CMP: Compare 0
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt
request will be generated if INTENCLR/SET.CMP0 is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare 0 interrupt flag.
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt
request will be generated if INTENCLR/SET.CMP0 is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare 0 interrupt flag.
Bit
7
6
5
4
3
2
1
0
OVF
SYNCRDY
CMP0
Access
R/W
R/W
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0