Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
26
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
10.
Processor And Architecture
10.1 Cortex M0+ Processor
The Atmel | SMART SAM D21 implements the ARM® Cortex™-M0+ processor, based on the ARMv6 Architecture and
Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and
upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1. For more
information refer to www.arm.com.
Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and
upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1. For more
information refer to www.arm.com.
10.1.1 Cortex M0+ Configuration
Note:
1. All software run in privileged mode only.
The ARM Cortex-M0+ core has two bus interfaces:
z
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system
memory, which includes flash and RAM.
memory, which includes flash and RAM.
z
Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.
10.1.2 Cortex-M0+ Peripherals
z
System Control Space (SCS)
z
The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference
Manual for details (
Manual for details (
www.arm.com)
.
z
System Timer (SysTick)
z
The System Timer is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer
to the Cortex-M0+ Technical Reference Manual for details (
to the Cortex-M0+ Technical Reference Manual for details (
www.arm.com)
.
z
Nested Vectored Interrupt Controller (NVIC)
Features
Configurable option
Atmel | SMART SAM D21
configuration
configuration
Interrupts
External interrupts 0-32
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Data endianness
Little-endian or big-endian
Little-endian
SysTick timer
Present or absent
Present
Number of watchpoint comparators
0, 1, 2
2
Number of breakpoint comparators
0, 1, 2, 3, 4
4
Halting debug support
Present or absent
Present
Multiplier
Fast or small
Fast (single cycle)
Single-cycle I/O port
Present or absent
Present
Wake-up interrupt controller
Supported or not supported
Not supported
Vector Table Offset Register
Present or absent
Present
Unprivileged/Privileged support
Present or absent
Memory Protection Unit
Not present or 8-region
Not present
Reset all registers
Present or absent
Absent
Instruction fetch width
16-bit only or mostly 32-bit
32-bit