Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

If a bus error is received from AHB slave during a DMA data transfer, the corresponding active channel is disabled and 
the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register 
(

.TERR) is set. If transfer error interrupt is enabled, optional error interrupt is generated. The transfer 

counter will not be decremented and its current value is written-back in the write-back memory section before the channel 
is disabled.

.VALID is zero) or when the channel is resumed and the DMA 

fetches the next descriptor with null address (

 is 0x00000000), the corresponding channel operation is 

suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register 
(

.SUSP) is set and the Channel Fetch Error bit in the Channel Status register (

enabled, optional suspend interrupt is generated.

A transaction can either consist of a single block transfer, or it can consist of several block transfers. When a transaction 
consist of several block transfers it is called linked descriptors.

 shows how linked descriptors work. When the first block transfer is completed on DMA channel 0, the DMAC 

fetches the next transfer descriptor which is pointed to by the value stored in the Next Descriptor Address (

transfer descriptor. When the block transfer for the last transfer descriptor is executed and 

the transaction is terminated. For further details on how the next descriptor is fetched from SRAM, refer to 

.

To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR=0x00000000 
indicating it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the 
address of the newly created descriptor.

In order to add descriptors to a list, the following actions must be performed:

1.

Before enabling a channel, the Suspend interrupt must be enabled

2.

Reserve memory space addresses to configure a new descriptor

3.

Configure the new descriptor

z

Set the next descriptor address (DESCADDR)

z

Set the destination address (DSTADDR)

z

Set the source address (SRCADDR)

z

Configure the block transfer control (BTCTRL) including

z

Optionally enable the Suspend block action

z

Set the descriptor VALID bit

4.

In the existing list and for the descriptor which has to be updated, set the VALID bit to zero

5.

Read DESCADDR from the Write-Back memory

DMA Channel 0

DMA Channel 1

PERIPHERAL 0

PERIPHERAL 1

{a,b}

{c,d}

DST Data Buffer

a

b

c

d