Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

278

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

The event output selections are available only for channels supporting event outputs. The pulse width of an event output 
from a channel is one AHB clock cycle.
The Channel Event Output Enable can be set in Control B register (

.EVOE). The Event Output Selection is 

available in each Descriptor Block Control location (

.EVOSEL). It is possible to generate events after each beat, 

burst or block transfer. To enable an event when the transaction is complete, the block event selection must be set in the 
last transfer descriptor only. 

 shows an example where the event output generation is enabled in the first 

block transfer, and disabled in the second block.

Transfers on any channel can be gracefully aborted by software, by disabling the corresponding DMA channel. It is also 
possible to abort all ongoing or pending transfers, by disabling the DMAC.

When DMAC disable request is detected:

z

Active channel with ongoing transfers will be disabled when the ongoing beat access is completed and the Write-
Back memory section is updated. This prevents transfer corruption before the channel is disabled.

z

All other enabled channels will be disabled in the next clock cycle. 

The corresponding Channel Enable bit in the Channel Control A register (CHCTRLA.ENABLE) is read as zero when the 
channel is disabled.

The corresponding DMAC Enable bit in the Control register (CTRL.DMAENABLE) is read as zero when the entire DMAC 
module is disabled.

A cyclic redundancy check (CRC) is an error detection technique used to find accidental errors in data. It is commonly 
used to determine whether the data during a transmission, or data present in data and programme memories has been 
corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be 
appended to the data and used as a checksum. When the same data are later received or read, the device or application 
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. 
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or 
simply not using the incorrect data.

Typically, a CRC-n applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any 
single alteration that spans no more than n bits of the data), and will detect the fraction 1-2

-n

 

of all longer error bursts. The 

Block Transfer

Data Transfer

Block Transfer

Event Output

Block Transfer

Data Transfer

Block Transfer

Event Output