Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
296
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.8.1.9 Priority Control 0
Name:
PRICTRL0
Offset:
0x14
Reset:
0x00000000
Property:
Write-Protected
z
Bit 31 – RRLVLEN3: Level 3 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 3 priority.
1: Round-robin scheduling scheme for channels with level 3 priority.
For details on scheduling schemes, refer to
0: Static scheduling scheme for channels with level 3 priority.
1: Round-robin scheduling scheme for channels with level 3 priority.
For details on scheduling schemes, refer to
z
Bits 30:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 27:24 – LVLPRI3[3:0]: Level 3 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3 is one) for priority level 3, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 3.
When static arbitration is enabled (PRICTRL0.RRLVLEN3 is zero) for priority level 3, and the value of this bit
group is non-zero, it will affect the static priority scheme. If the value of this bit group is x, channel x will have the
highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum
number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from
channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN3 written to zero).
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3 is one) for priority level 3, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 3.
When static arbitration is enabled (PRICTRL0.RRLVLEN3 is zero) for priority level 3, and the value of this bit
group is non-zero, it will affect the static priority scheme. If the value of this bit group is x, channel x will have the
highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum
number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from
channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN3 written to zero).
Bit
31
30
29
28
27
26
25
24
RRLVLEN3
LVLPRI3[3:0]
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RRLVLEN2
LVLPRI2[3:0]
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
RRLVLEN1
LVLPRI1[3:0]
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RRLVLEN0
LVLPRI0[3:0]
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0