Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
299
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.8.1.10 Interrupt Pending
This register allows the user to identify the lowest DMA channel with pending interrupt.
Name:
INTPEND
Offset:
0x20
Reset:
0x0000
Property:
-
z
Bit 15 – PEND: Pending
This bit is read one when the channel selected by Channel ID field (ID) is pending.
This bit is read one when the channel selected by Channel ID field (ID) is pending.
z
Bit 14 – BUSY: Busy
This bit is read one when the channel selected by Channel ID field (ID) is busy.
This bit is read one when the channel selected by Channel ID field (ID) is busy.
z
Bit 13 – FERR: Fetch Error
This bit is read one when the channel selected by Channel ID field (ID) fetched an invalid descriptor.
This bit is read one when the channel selected by Channel ID field (ID) fetched an invalid descriptor.
z
Bits 12:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 10 – SUSP: Channel Suspend
This bit is read one when the channel selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Suspend interrupt flag.
This bit is read one when the channel selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Suspend interrupt flag.
z
Bit 9 – TCMPL: Transfer Complete
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag.
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag.
z
Bit 8 – TERR: Transfer Error
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Transfer Error interrupt flag.
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Transfer Error interrupt flag.
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit
15
14
13
12
11
10
9
8
PEND
BUSY
FERR
SUSP
TCMPL
TERR
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0