Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
317
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.8.1.23 Channel Status
Name:
CHSTATUS
Offset:
0x4F
Reset:
0x00
Property:
-
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – FERR: Fetch Error
This bit is cleared when the software resume command is executed.
This bit is set when an invalid descriptor is fetched.
This bit is cleared when the software resume command is executed.
This bit is set when an invalid descriptor is fetched.
z
Bit 1 – BUSY: Channel Busy
This bit is cleared when the channel trigger action is complete, when a bus error is detected or when the channel is
disabled.
This bit is set when the DMA channel starts a DMA transfer.
This bit is cleared when the channel trigger action is complete, when a bus error is detected or when the channel is
disabled.
This bit is set when the DMA channel starts a DMA transfer.
z
Bit 0 – PEND: Channel Pending
This bit is cleared when trigger execution defined by channel trigger action settings is started, when a bus error is
detected or when the channel is disabled. For details on trigger action settings, refer to
This bit is cleared when trigger execution defined by channel trigger action settings is started, when a bus error is
detected or when the channel is disabled. For details on trigger action settings, refer to
This bit is set when a transfer is pending on the DMA channel.
Bit
7
6
5
4
3
2
1
0
FERR
BUSY
PEND
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0