Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
324
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.8.2.5 Next Descriptor Address
The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name:
DESCADDR
Offset:
0x0C
z
Bits 31:0 – DESCADDR[31:0]: Next Descriptor Address
This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of
this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next trans-
fer descriptor.
This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of
this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next trans-
fer descriptor.
Bit
31
30
29
28
27
26
25
24
DESCADDR[31:24]
Bit
23
22
21
20
19
18
17
16
DESCADDR[23:16]
Bit
15
14
13
12
11
10
9
8
DESCADDR[15:8]
Bit
7
6
5
4
3
2
1
0
DESCADDR[7:0]