Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
38
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
10.6.2.3 PAC2 Register Description
Write Protect Clear
Name:
WPCLR
Offset:
0x00
Reset:
0x00800000
Property:
-
z
Bits 31:21 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
reset value when this register is written. These bits will always return reset value when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
reset value when this register is written. These bits will always return reset value when read.
z
Bits 20:1 – I2S, PTC, DAC, AC, ADC, TC7, TC6, TC5, TC4, TC3, TCC2, TCC1, TCC0, SERCOM5, SERCOM4,
SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
I2S
PTC
DAC
AC
ADC
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
1
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TC7
TC6
TC5
TC4
TC3
TCC2
TCC1
TCC0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SERCOM5
SERCOM4
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
0
0