Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

Product codes
ATSAMD21-XPRO
Page of 1018
426
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
24.6.3 Additional Features
24.6.3.1  Address Match and Mask
The SERCOM address match and mask feature is capable of matching one address with a mask, two unique addresses 
or a range of addresses, based on the mode selected. The match uses seven or eight bits, depending on the mode.
Address With Mask
An address written to the Address bits in the Address register (ADDR.ADDR) with a mask written to the Address Mask 
bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not included in 
the match. Note that setting the ADDR.ADDRMASK to all zeros will match a single unique address, while setting 
ADDR.ADDRMASK to all ones will result in all addresses being accepted.
Figure 24-4. Address With Mask
Two Unique Addresses
The two addresses written to ADDR and ADDRMASK will cause a match.
Figure 24-5. Two Unique Addresses
Address Range
The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR 
and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and 
ADDR.ADDRMASK acting as the lower limit.
Figure 24-6. Address Range
24.6.4 DMA Operation
Not applicable. 
rx shift register
ADDRMASK
ADDR
==
Match
ADDRMASK
rx shift register
ADDR
==
Match
==
ADDRMASK
rx shift register
ADDR
==
Match