Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
454
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
25.8.5 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x14
Reset:
0x00
Property:
Write-Protected
z
Bit 7– ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
z
Bit 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 5 – RXBRK: Receive Break Interrupt Enable
0: Receive Break interrupt is disabled.
1: Receive Break interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break
interrupt.
0: Receive Break interrupt is disabled.
1: Receive Break interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break
interrupt.
z
Bit 4 – CTSIC: Clear to Send Input Change Interrupt Enable
0: Clear To Send Input Change interrupt is disabled.
1: Clear To Send Input Change interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To
Send Input Change interrupt.
0: Clear To Send Input Change interrupt is disabled.
1: Clear To Send Input Change interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To
Send Input Change interrupt.
z
Bit 3 – RXS: Receive Start Interrupt Enable
0: Receive Start interrupt is disabled.
1: Receive Start interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt.
0: Receive Start interrupt is disabled.
1: Receive Start interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt.
z
Bit 2 – RXC: Receive Complete Interrupt Enable
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Bit
7
6
5
4
3
2
1
0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
Access
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0