Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

Data are always shifted from master to slave on the master output, slave input line (MOSI), and from slave to master on 
the master input, slave output line (MISO). The master signals the end of the transaction by pulling the _SS line high.

As each character is shifted out from the master, another character is shifted in from the slave.

The following registers are enable-protected, meaning that they can only be written when the SPI is disabled 
(CTRL.ENABLE is zero):

z

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)

z

Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)

z

Baud register (BAUD)

z

Address register (ADDR)

Any writes to these registers when the SPI is enabled or is being enabled (CTRLA.ENABLE is one) will be discarded. 
Writes to these registers while the SPI is being disabled will be completed after the disabling is complete.

Enable-protection is denoted by the Enable-Protection property in the register description.

Before the SPI is enabled, it must be configured, as outlined by the following steps:

z

SPI mode in master or slave operation must be selected by writing 0x2 or 0x3 to the Operating Mode bit group in 
the Control A register (CTRLA.MODE)

z

Transfer mode must be selected by writing the Clock Polarity bit and the Clock Phase bit in the Control A register 
(CTRLA.CPOL and CTRLA.CPHA)

z

Transaction format must be selected by writing the Frame Format bit group in the Control A register 
(CTRLA.FORM)

z

SERCOM pad to use for the receiver must be selected by writing the Data In Pinout bit group in the Control A 
register (CTRLA.DIPO)

z

SERCOM pads to use for the transmitter, slave select and serial clock must be selected by writing the Data Out 
Pinout bit group in the Control A register (CTRLA.DOPO)

z

Character size must be selected by writing the Character Size bit group in the Control B register (CTRLB.CHSIZE)

z

Data direction must be selected by writing the Data Order bit in the Control A register (CTRLA.DORD) 

z

If the SPI is used in master mode, the Baud register (BAUD) must be written to generate the desired baud rate

z

If the SPI is used in master mode and Hardware SS control is required, the Master Slave Select Enable bit in 
CTRLB register (CTRLB.MSSEN) should be set to 1.

z

The receiver can be enabled by writing a one to the Receiver Enable bit in the Control B register (CTRLB.RXEN)

The SPI is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The SPI is disabled by 
writing a zero to CTRLA.ENABLE.

The SPI is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the 
SPI, except DBGCTRL, will be reset to their initial state, and the SPI will be disabled. Refer to CTRLA for details.

In SPI master operation (CTRLA.MODE is 0x3), the serial clock (SCK) is generated internally using the SERCOM baud-
rate generator. When used in SPI mode, the baud-rate generator is set to synchronous mode, and the 8-bit Baud register 
(BAUD) value is used to generate SCK, clocking the shift register. Refer to 

 for more details.

In SPI slave operation (CTRLA.MODE is 0x2), the clock is provided by an external master on the SCK pin. This clock is 
used to directly clock the SPI shift register.