Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in 
the Interrupt Flag Status and Clear register (INTFLAG.TXC) is set. When the transaction is finished, the master must 
indicate this to the slave by pulling the _SS line high. If Master Slave Select Enable (CTRLB.MSSEN) is set to zero, the 
software must pull the _SS line high. 

When configured as a slave (CTRLA.MODE is 0x2), the SPI interface will remain inactive, with the MISO line tri-stated as 
long as the _SS pin is pulled high. Software may update the contents of DATA at any time, as long as the Data Register 
Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set.

When _SS is pulled low and SCK is running, the slave will sample and shift out data according to the transaction mode 
set. When the contents of TxDATA have been loaded into the shift register, INTFLAG.DRE is set, and new data can be 
written to DATA. Similar to the master, the slave will receive one character for each character transmitted. On the same 
clock cycle as the last data bit of a character is received, the character will be transferred into the two-level receive buffer. 
The received character can be retrieved from DATA when Receive Complete interrupt flag (INTFLAG.RXC) is set.

When the master pulls the _SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt 
Flag Status and Clear register (INTFLAG.TXC) is set.

Once DATA is written, it takes up to three SCK clock cycles before the content of DATA is ready to be loaded into the 
shift register. When the content of DATA is ready to be loaded, this will happen on the next character boundary. As a 
consequence, the first character transferred in a SPI transaction will not be the content of DATA. This can be avoided by 
using the preloading feature.

When transmitting several characters in one SPI transaction, the data has to be written to DATA while there are at least 
three SCK clock cycles left in the current character transmission. If this criteria is not met, then the previous character 
received will be transmitted. 

After the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.

The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register 
(STATUS). Upon error detection, the bit will be set until it is cleared by writing a one to it. The bit is also automatically 
cleared when the receiver is disabled.

There are two methods for buffer overflow notification. When the immediate buffer overflow notification bit (CTRLA.IBON) 
is set, STATUS.BUFOVF is set immediately upon buffer overflow. Software can then empty the receive FIFO by reading 
RxDATA until the receive complete interrupt flag (INTFLAG.RXC) goes low.

When CTRLA.IBON is zero, the buffer overflow condition travels with data through the receive FIFO. After the received 
data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero.

When the SPI is configured for slave operation (CTRLA.MODE is 0x2) with address recognition (CTRLA.FORM is 0x2), 
the SERCOM address recognition logic is enabled. When address recognition is enabled, the first character in a 
transaction is checked for an address match. If there is a match, then the Receive Complete Interrupt flag in the Interrupt 
Flag Status and Clear register (INTFLAG.RXC) is set, the MISO output is enabled and the transaction is processed. If 
there is no match, the transaction is ignored.

If the device is in sleep mode, an address match can wake up the device in order to process the transaction. If the 
address does not match, then the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits 
of the shift register are checked against the Address register (ADDR).

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