Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
480
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
26.8.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00000000
Property:
Write-Protected, Enable-Protected, Write-Synchronized
z
Bit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 30 – DORD: Data Order
This bit indicates the data order when a character is shifted out from the Data register.
0: MSB is transferred first.
1: LSB is transferred first.
This bit is not synchronized.
This bit indicates the data order when a character is shifted out from the Data register.
0: MSB is transferred first.
1: LSB is transferred first.
This bit is not synchronized.
z
Bit 29 – CPOL: Clock Polarity
In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.
0: SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge.
1: SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge.
This bit is not synchronized.
In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.
0: SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge.
1: SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge.
This bit is not synchronized.
z
Bit 28 – CPHA: Clock Phase
In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.
In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.
Bit
31
30
29
28
27
26
25
24
DORD
CPOL
CPHA
FORM[3:0]
Access
R
R/W
R/W
R/W R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIPO[1:0]
DOPO[1:0]
Access
R
R
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
IBON
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
MODE[2:0]
ENABLE
SWRST
Access
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0