Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

500

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

 for details on the pin mapping for this peripheral. One signal 

can be mapped on several pins. Note that not all the pins are I

2

C pins. Refer to 

 for details on the pin type for 

each pin. 

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

Using the SERCOM’s I/O lines requires the I/O pins to be configured. Refer to 

 for details. 

The I

2

C will continue to operate in any sleep mode where the selected source clock is running. I

2

C interrupts can be used 

to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep 
modes. Refer to 

 for details on the different sleep modes. 

The SERCOM bus clock (CLK_SERCOMx_APB, where i represents the specific SERCOM instance number) is enabled 
by default, and can be enabled and disabled in the Power Manager. Refer to 

details. 

The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled in the Power 
Manager. Refer to 

 for details. 

Two generic clocks are used by the SERCOM (GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW). The core clock 
(GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a master, while the slow clock 
(GCLK_SERCOM_SLOW) is required only for certain functions. These clocks must be configured and enabled in the 
Generic Clock Controller (GCLK) before using the SERCOM. Refer to 

 for 

details. 

These generic clocks are asynchronous to the SERCOM bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, 
writes to certain registers will require synchronization between the clock domains. Refer to the 

 section for further details. 

The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires the DMA 
controller to be configured first. Refer to 

 for details.

The interrupt request line is connected to the Interrupt Controller. Using the I

2

C interrupts requires the Interrupt Controller 

 for details.

PAD[0]

Digital I/O

SDA

PAD[1]

Digital I/O

SCL

PAD[2]

Digital I/O

SDA_OUT (4-wire)

PAD[3]

Digital I/O

SDC_OUT (4-wire)