Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is then 
used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for master reads) and a STOP.

If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be automatically 
generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt.

The I

2

C master generates the following requests:

z

Read data received (RX): The request is set when master read data is received. The request is cleared when 
DATA is read.

z

Write data needed for transmit (TX): The request is set when data is needed for a master write operation. The 
request is cleared when DATA is written.

The I

2

C slave has the following interrupt sources: 

z

Error (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.

z

Data Ready (DRDY): this is an asynchronous interrupt and can be used to wake-up the device from any sleep 
mode.

z

Address Match (AMATCH): this is an asynchronous interrupt and can be used to wake-up the device from any 
sleep mode.

z

Stop Received (PREC): this is an asynchronous interrupt and can be used to wake-up the device from any sleep 
mode.

The I

2

C master has the following interrupt sources: 

z

Error (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.

z

Slave on Bus (SB): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.

z

Master on Bus (MB): this is an asynchronous interrupt and can be used to wake-up the device from any sleep 
mode.

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear 
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one 
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the 
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt 
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is 
cleared, the interrupt is disabled or the I

2

C is reset. See 

 for details on how to clear interrupt flags. 

The I

2

C has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine 

which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 

Not applicable.

During I

2

C master operation, the generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the 

Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is one, the GLK_SERCOMx_CORE will also run in 
standby sleep mode. Any interrupt can wake up the device.

If CTRLA.RUNSTDBY is zero during I

2

C master operation, the GLK_SERCOMx_CORE will be disabled when an 

ongoing transaction is finished. Any interrupt can wake up the device.

During I

2

C slave operation, writing a one to CTRLA.RUNSTDBY will allow the Address Match interrupt to wake up the 

device. 

In I

2

C slave operation, all receptions will be dropped when CTRLA.RUNSTDBY is zero.