Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
536
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
27.8.1.7 Synchronization Busy
Name:
SYNCBUSY
Offset:
0x1C
Reset:
0x00000000
Property:
z
Bits 31:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNC-
BUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and
an APB error will be generated.
0: Enable synchronization is not busy.
1: Enable synchronization is busy.
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNC-
BUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and
an APB error will be generated.
0: Enable synchronization is not busy.
1: Enable synchronization is busy.
z
Bit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit
will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be generated.
0: SWRST synchronization is not busy.
1: SWRST synchronization is busy.
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit
will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be generated.
0: SWRST synchronization is not busy.
1: SWRST synchronization is busy.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ENABLE
SWRST
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0