Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
540
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
27.8.2 I
2
C Master Register Description
27.8.2.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00000000
Property:
Write-Protected, Enable-Protected, Write-Synchronized
z
Bit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 30 – LOWTOUT: SCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the master will release its clock hold, if
enabled, and complete the current transaction. A stop condition will automatically be transmitted.
INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT
and STATUS.BUSERR status bits will be set.
0: Time-out disabled.
1: Time-out enabled.
This bit is not synchronized.
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the master will release its clock hold, if
enabled, and complete the current transaction. A stop condition will automatically be transmitted.
INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT
and STATUS.BUSERR status bits will be set.
0: Time-out disabled.
1: Time-out enabled.
This bit is not synchronized.
z
Bits 29:28 – INACTOUT[1:0]: Inactive Time-Out
If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic
will be set to idle. An inactive bus arise when either an I
If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic
will be set to idle. An inactive bus arise when either an I
2
C master or slave is holding the SCL low. The available
time-outs are given in
Bit
31
30
29
28
27
26
25
24
LOWTOUT
INACTOUT[1:0]
SCLSM
SPEED[1:0]
Access
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
SEXTTOEN
MEXTTOEN
SDAHOLD[1:0]
PINOUT
Access
R/W
R/W
R/W
R/W
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
MODE[2:0]=101
ENABLE
SWRST
Access
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0