Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
557
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
27.8.2.9 Address
Name:
ADDR
Offset:
0x24
Reset:
0x0000
Property:
Write-Synchronized
z
Bits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 23:16 – LEN[7:0]: Transaction Length
For DMA operation, this field represents the data length of the transaction from 0 to 255 bytes. The transaction
length enable (ADDR.LENEN) must be written to 1 for automatic transaction length to be used. After ADDR.LEN
bytes have been transmitted or received, a NACK (for master reads) and STOP are automatically generated.
For DMA operation, this field represents the data length of the transaction from 0 to 255 bytes. The transaction
length enable (ADDR.LENEN) must be written to 1 for automatic transaction length to be used. After ADDR.LEN
bytes have been transmitted or received, a NACK (for master reads) and STOP are automatically generated.
z
Bit 15 – TENBITEN: Ten Bit Addressing Enable
This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit
address transmission.
0: 10-bit addressing disabled.
1: 10-bit addressing enabled.
This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit
address transmission.
0: 10-bit addressing disabled.
1: 10-bit addressing enabled.
z
Bit 14 – HS: High Speed
This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written
simultaneously with ADDR for a high speed transfer.
0: High-speed transfer disabled.
This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written
simultaneously with ADDR for a high speed transfer.
0: High-speed transfer disabled.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
LEN[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TENBITEN
HS
LENEN
ADDR[10:8]
Access
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ADDR[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0