Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
567
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Mono format can be enabled by setting SERCTRLm.MONO bit.
I
2
S support different data frame formats:
z
2-channel I
2
S with Word Select
z
1- to 8-slot Time Division Multiplexed (TDM) with Frame Sync and individually enabled slots
z
1- or 2-channel Pulse Density Modulation (PDM) reception for MEMS microphones
z
1-channel burst transfer with non-periodic Frame Sync
In 2 channel I
2
S mode, number of slots configured is one or two and successive data words corresponds to left and right
channel. Left and right channel is identified by polarity of Word Select signal (FSn signal). Each frame consists of one or
two data word. In case of compact stereo format is used, the number of slot can be one. In case of 32-bit slot size is
used, the number of slot can be two.
two data word. In case of compact stereo format is used, the number of slot can be one. In case of 32-bit slot size is
used, the number of slot can be two.
In TDM format, number slots can be configured up to 8 slots. If 4 slots are configured, each frame consists of 4 data
words.
words.
In PDM format, continuous 1-bit data samples are available on the SDm line for each SCKn rising and SCKn falling edge
as in case of a MEMS microphone with PDM interface.
as in case of a MEMS microphone with PDM interface.
1-channel burst transfer with non-periodic Frame Sync mode is useful typically for passing control non-auto data as in
case of DSP. In Burst mode, a single Data transfer starts at each Frame Sync pulse, and these pulses are 1-bit wide and
occur only when a Data transfer is requested.
case of DSP. In Burst mode, a single Data transfer starts at each Frame Sync pulse, and these pulses are 1-bit wide and
occur only when a Data transfer is requested.
describes more about
frame/data formats and register settings required for different I
2
S applications.
Figure 28-3. I
2
S Functional Block Diagram
28.6.1.1 Initialization
The I
2
S features two Clock Units, two Serializers configurable as Receiver or Transmitter. The two Serializers can either
share the same Clock Unit or use separate Clock Units.
Before enabling the I
2
S, the following registers must be configured:
z
Clock Control registers (CLKCTRLn)
z
Serializer Control registers (SERCTRLm)
CLK_I2S_APB
GCLK_I2S_n
MCKn
SCKn
FSn
SDm
Clock Unit n
CLKCTRLn
APB / DMA
Interface
Rx/Tx Frame
Sequencer
Rx/Tx
Word
FSM
Rx/Tx
Word
Serializer
Tx Word
Formatting
Rx Word
Formatting
SERCTRLn
Serializer m