Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
58
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
12.13.2 Status A
Name:
STATUSA
Offset:
0x0001
Reset:
0x00
Property:
Write-Protected
z
Bits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 4 – PERR: Protection Error
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Protection Error bit.
This bit is set when a command that is not allowed in protected state is issued.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Protection Error bit.
This bit is set when a command that is not allowed in protected state is issued.
z
Bit 3 – FAIL: Failure
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
z
Bit 2 – BERR: Bus Error
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
z
Bit 1 – CRSTEXT: CPU Reset Phase Extension
Writing a zero to this bit has no effect.
Writing a one to this bit clears the CPU Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the CPU Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.
z
Bit 0 – DONE: Done
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
Bit
7
6
5
4
3
2
1
0
PERR
FAIL
BERR
CRSTEXT
DONE
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0