Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
583
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
28.9.2 Clock Unit n Control
Name:
CLKCTRLn
Offset:
0x04+n*0x4 [n=0..1]
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected
z
Bit 31 – MCKOUTINV: Master Clock Output Invert
0: The Master Clock n is output without inversion.
1: The Master Clock n is inverted before being output.
0: The Master Clock n is output without inversion.
1: The Master Clock n is inverted before being output.
z
Bit 30 – SCKOUTINV: Serial Clock Output Invert
0: The Serial Clock n is output without inversion.
1: The Serial Clock n is inverted before being output.
0: The Serial Clock n is output without inversion.
1: The Serial Clock n is inverted before being output.
z
Bit 29 – FSOUTINV: Frame Sync Output Invert
0: The Frame Sync n is output without inversion.
1: The Frame Sync n is inverted before being output.
0: The Frame Sync n is output without inversion.
1: The Frame Sync n is inverted before being output.
z
Bits 28:24 – MCKOUTDIV[4:0]: Master Clock Output Division Factor
The generic clock selected by MCKSEL is divided by (MCKOUTDIV + 1) to obtain the Master Clock n output.
The generic clock selected by MCKSEL is divided by (MCKOUTDIV + 1) to obtain the Master Clock n output.
z
Bits 23:19 – MCKDIV[4:0]: Master Clock Division Factor
The Master Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n.
The Master Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n.
z
Bit 18 – MCKEN: Master Clock Enable
0: The Master Clock n division and output is disabled.
0: The Master Clock n division and output is disabled.
Bit
31
30
29
28
27
26
25
24
MCKOUTINV
SCKOUTINV
FSOUTINV
MCKOUTDIV[4:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
MCKDIV[4:0]
MCKEN
MCKSEL
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
SCKSEL
FSINV
FSSEL
Access
R
R
R
R/W
R/W
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BITDELAY
FSWIDTH[1:0]
NBSLOTS[2:0]
SLOTSIZE[1:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0