Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
592
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
28.9.6 Synchronization Busy
Name:
SYNCBUSY
Offset:
0x18
Reset:
0x0000
Property:
-
z
Bits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 9:8 – DATAx [x=1..0]: Data x Synchronization Status
Bit DATAx is cleared when the synchronization of DATA Holding register (DATAx) between the clock domains is
complete.
Bit DATAx is set when the synchronization of DATA Holding register (DATAx) between the clock domains is
started.
Bit DATAx is cleared when the synchronization of DATA Holding register (DATAx) between the clock domains is
complete.
Bit DATAx is set when the synchronization of DATA Holding register (DATAx) between the clock domains is
started.
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:4 – SERENx [x=1..0]: Serializer x Enable Synchronization Status
Bit SERENx is cleared when the synchronization of CTRLA.SERENx bit between the clock domains is complete.
Bit SERENx is set when the synchronization of CTRLA.SERENx bit between the clock domains is started.
Bit SERENx is cleared when the synchronization of CTRLA.SERENx bit between the clock domains is complete.
Bit SERENx is set when the synchronization of CTRLA.SERENx bit between the clock domains is started.
z
Bits 3:2 – CKENx [x=1..0]: Clock Unit x Enable Synchronization Status
Bit CKENx is cleared when the synchronization of CTRLA.CKENx bit between the clock domains is complete.
Bit CKENx is set when the synchronization of CTRLA.CKENx bit between the clock domains is started.
Bit CKENx is cleared when the synchronization of CTRLA.CKENx bit between the clock domains is complete.
Bit CKENx is set when the synchronization of CTRLA.CKENx bit between the clock domains is started.
z
Bit 1 – ENABLE: Enable Synchronization Status
This bit is cleared when the synchronization of CTRLA.ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of CTRLA.ENABLE bit between the clock domains is started.
This bit is cleared when the synchronization of CTRLA.ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of CTRLA.ENABLE bit between the clock domains is started.
z
Bit 0 – SWRST: Software Reset Synchronization Status
This bit is cleared when the synchronization of CTRLA.SWRST bit between the clock domains is complete.
This bit is set when the synchronization of CTRLA.SWRST bit between the clock domains is started.
This bit is cleared when the synchronization of CTRLA.SWRST bit between the clock domains is complete.
This bit is set when the synchronization of CTRLA.SWRST bit between the clock domains is started.
Bit
15
14
13
12
11
10
9
8
DATA1
DATA0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SEREN1
SEREN0
CKEN1
CKEN0
ENABLE
SWRST
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0