Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
616
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
29.8.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x0000
Property:
Write-Protected, Enable-Protected, Write-Synchronized
z
Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 13:12 – PRESCSYNC[1:0]: Prescaler and Counter Synchronization
These bits select whether on start or retrigger event the counter should wrap around on the next GCLK_TCx clock
or the next prescaled GCLK_TCx clock. It’s also possible to reset the prescaler.
The options are as shown in
These bits select whether on start or retrigger event the counter should wrap around on the next GCLK_TCx clock
or the next prescaled GCLK_TCx clock. It’s also possible to reset the prescaler.
The options are as shown in
These bits are not synchronized.
Table 29-5. Prescaler and Counter Synchronization
z
Bit 11 – RUNSTDBY: Run in Standby
This bit is used to keep the TC running in standby mode:
0: The TC is halted in standby.
1: The TC continues to run in standby.
This bit is not synchronized.
This bit is used to keep the TC running in standby mode:
0: The TC is halted in standby.
1: The TC continues to run in standby.
This bit is not synchronized.
z
Bits 10:8 – PRESCALER[2:0]: Prescaler
These bits select the counter prescaler factor, as shown in
These bits select the counter prescaler factor, as shown in
These bits are not synchronized.
Bit
15
14
13
12
11
10
9
8
PRESCSYNC[1:0]
RUNSTDBY
PRESCALER[2:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WAVEGEN[1:0]
MODE[1:0]
ENABLE
SWRST
Access
R
R/W
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Value
Name
Description
0x0
GCLK
Reload or reset the counter on next generic clock
0x1
PRESC
Reload or reset the counter on next prescaler clock
0x2
RESYNC
Reload or reset the counter on next generic clock. Reset the prescaler counter
0x3
-
Reserved