Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
629
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
29.8.9 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x0D
Reset:
0x00
Property:
Write-Protected
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:4 – MCx: Match or Capture Channel x Interrupt Enable
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables
the Match or Capture Channel x interrupt.
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables
the Match or Capture Channel x interrupt.
z
Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Disable/Enable bit, which enables the Syn-
chronization Ready interrupt.
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Disable/Enable bit, which enables the Syn-
chronization Ready interrupt.
z
Bit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 1 – ERR: Error Interrupt Enable
0: The Error interrupt is disabled.
1: The Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt bit, which enables the Error interrupt.
0: The Error interrupt is disabled.
1: The Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt bit, which enables the Error interrupt.
z
Bit 0 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt.
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt.
Bit
7
6
5
4
3
2
1
0
MC1
MC0
SYNCRDY
ERR
OVF
Access
R
R
R/W
R/W
R/W
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0