Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

The following registers are enable-protected, meaning that it can only be written when the TCC is disabled 
(CTRLA.ENABLE is zero): 

z

Control A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset 
(SWRST) bits

z

Recoverable Fault n Control register (FCTRLA and FCTRLB)

z

Waveform Extension Control register (WEXCTRL)

z

Drive Control register (DRVCTRL)

z

Event Control register

Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to one, but not 
at the same time as CTRLA.ENABLE is written to zero.

Enable-protection is denoted by the Enable-Protected property in the register description.

Before the TCC is enabled, it must be configured as outlined by the following steps:

z

Enable the TCC bus clock (CLK_TCCx_APB) first

z

If Capture mode is required, enable the channel in capture mode by writing a one to Capture Enable bit in 
Control A register (CTRLA.CAPTEN)

Optionally, the following configurations can be set before or after enabling TCC:

z

Select PRESCALER setting in the Control A register (CTRLA.PRESCALER)

z

Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC)

z

If down-counting operation must be enabled, write a one to the Counter Direction bit in the Control B Set 
register (CTRLBSET.DIR)

z

Select the Waveform Generation operation in WAVE register (WAVE.WAVEGEN)

z

Select the Waveform Output Polarity in the WAVE register (WAVE.POL)

z

The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable 
bit group in the Driver register (DRVCTRL.INVEN)

The TCC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The TCC is disabled 
by writing a zero to CTRLA.ENABLE.

The TCC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the 
TCC, except DBGCTRL, will be reset to their initial state, and the TCC will be disabled. Refer to 

details.

The TCC should be disabled before the TCC is reset to avoid undefined behavior.

The GCLK_TCCx is fed into the internal prescaler. Prescaler output intervals from 1 to 1/1024 are available. For a 
complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A 
register (CTRLA.PRESCALER).

The prescaler consists of a counter that counts to the selected prescaler value, whereupon the output of the prescaler 
toggles. When the prescaler is set to a value greater than one, it is necessary to choose whether the prescaler should 
reset its value to zero or continue counting from its current value on the occurrence of an external re-trigger. It is also 
necessary to choose whether the TCC counter should wrap around on the next GCLK_TCC clock pulse or the next 
prescaled clock pulse (CLK_TCC_CNT in 

). To do this, use the Prescaler and Counter synchronization bit 

group in the Control A register (CTRLA.PRESYNC). If the counter is set to count events from the event system, these will 
not pass through the prescaler.