Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
679
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.2 Control B Clear
This register allows the user to change the below mentioned functionalities without doing a read-modify-write operation.
Changes in this register will also be reflected in the Control B Set (CTRLBSET) register.
Changes in this register will also be reflected in the Control B Set (CTRLBSET) register.
Name:
CTRLBCLR
Offset:
0x04
Reset:
0x00
Property:
Read-Synchronized, Write-Protected, Write-Synchronized
z
Bits 7:5 – CMD[2:0]: TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command
has been executed, the CMD bit field will read back zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing a zero to this bit group has no effect.
Writing a valid value to these bits will clear the corresponding pending command.
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command
has been executed, the CMD bit field will read back zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing a zero to this bit group has no effect.
Writing a valid value to these bits will clear the corresponding pending command.
Table 30-9. TCC Command
z
Bits 4:3 – IDXCMD[1:0]: Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation, according to the
following table. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is
updated and the IDXCMD command is cleared.
Writing a zero to this field has no effect.
Writing a valid value to this field will clear the pending command.
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation, according to the
following table. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is
updated and the IDXCMD command is cleared.
Writing a zero to this field has no effect.
Writing a valid value to this field will clear the pending command.
Table 30-10. Ramp Index Command
Bit
7
6
5
4
3
2
1
0
CMD[2:0]
IDXCMD[1:0]
ONESHOT
LUPD
DIR
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
CMD[2:0]
Name
Description
0x0
NONE
No action
0x1
RETRIGGER
Clear start, restart or retrigger
0x2
STOP
Force stop
0x3
UPDATE
Force update of double buffered registers
0x4
READSYNC
Force COUNT read synchronization
0x5-0x7
Reserved
IDXCMD[1:0]
Name
Description
0x0
DISABLE
Command disabled: Index toggles between cycles A and B