Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
695
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.9 Debug Control
Name:
DBGCTRL
Offset:
0x1E
Reset:
0x00
Property:
Write-Protected
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – FDDBD: Fault Detection on Debug Break Detection
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
By default this bit is zero, the on-chip debug (OCD) fault protection is enabled. OCD break request from the OCD
system will trigger non-recoverable fault. When this bit is set, OCD fault protection is disabled and OCD break
request will not trigger a fault.
0: No faults are generated when TCC is halted in debug mode.
1: A non recoverable fault is generated and DFS flag is set when TCC is halted in debug mode.
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
By default this bit is zero, the on-chip debug (OCD) fault protection is enabled. OCD break request from the OCD
system will trigger non-recoverable fault. When this bit is set, OCD fault protection is disabled and OCD break
request will not trigger a fault.
0: No faults are generated when TCC is halted in debug mode.
1: A non recoverable fault is generated and DFS flag is set when TCC is halted in debug mode.
z
Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 0 – DBGRUN: Debug Running Mode
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
0: The TCC is halted when the device is halted in debug mode.
1: The TCC continues normal operation when the device is halted in debug mode.
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
0: The TCC is halted when the device is halted in debug mode.
1: The TCC continues normal operation when the device is halted in debug mode.
Bit
7
6
5
4
3
2
1
0
FDDBD
DBGRUN
Access
R
R
R
R
R
R/W
R
R/W
Reset
0
0
0
0
0
0
0
0