Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
699
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.11 Interrupt Enable Clear
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set (INTENSET) register.
will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name:
INTENCLR
Offset:
0x24
Reset:
0x00000000
Property:
Write-Protected
z
Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 19:16 – MCx [x=3..0]: Match or Capture Channel x Interrupt Enable
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
z
Bit 15 – FAULT1: Non-Recoverable Fault 1 Interrupt Enable
0: The Non-Recoverable Fault 1 interrupt is disabled.
1: The Non-Recoverable Fault 1 interrupt is enabled.
Writing a zero to this bit has no effect.
0: The Non-Recoverable Fault 1 interrupt is disabled.
1: The Non-Recoverable Fault 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
MC3
MC2
MC1
MC0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
FAULT1
FAULT0
FAULTB
FAULTA
DFS
Access
R/W
R/W
R/W
R/W
R/W
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ERR
CNT
TRG
OVF
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0