Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

Product codes
ATSAMD21-XPRO
Page of 1018
705
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.13 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x2C
Reset:
0x00000000
Property:
-
z
Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bits 19:16 – MCx [x=3..0]: Match or Capture x
This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx regis-
ter contain a valid capture value.
Writing a zero to one of these bits has no effect.
Writing a one to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In Capture operation, this flag is automatically cleared when CCx register is read.
z
Bit 15 – FAULT1: Non-Recoverable Fault 1
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 1 occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Non-Recoverable Fault 1 interrupt flag.
z
Bit 14 – FAULT0: Non-Recoverable Fault 0
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 0 occurs.
Writing a zero to this bit has no effect.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
MC3
MC2
MC1
MC0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
FAULT1
FAULT0
FAULTB
FAULTA
DFS
Access
R/W
R/W
R/W
R/W
R/W
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ERR
CNT
TRG
OVF
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0