Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
729
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.23 Compare and Capture Buffer
Mode:
DITH4
Name:
CCBn
Offset:
0x70+n*0x4 [n=0..3]
Reset:
0x00000000
Property:
-
z
Bits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 23:4 – CCB[19:0]: Channel Compare/Capture Buffer Value
These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the
associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corre-
sponding CCBVx status bit.
The number of bits in this field corresponds to the size of the counter.
These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the
associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corre-
sponding CCBVx status bit.
The number of bits in this field corresponds to the size of the counter.
z
Bits 3:0 – DITHERCYB[3:0]: Dithering Buffer Cycle Number
These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the CCx.DITHERCY bits on an UPDATE condition.
These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the CCx.DITHERCY bits on an UPDATE condition.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CCB[19:12]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
CCB[11:4]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CCB[3:0]
DITHERCYB[3:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0