Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

This section gives an overview of the USB module Host operation during normal transactions. For more details on 
general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1.

Prior to device detection the software must set the VBUS is OK bit in CTRLB (CTRLB.VBUSOK) register when the VBUS 
is available. This notifies the USB host that USB operations can be started. When the bit CTRLB.VBUSOK is zero and 
even if the USB HOST is configured and enabled, host operation is halted. Setting the bit CTRLB.VBUSOK will allow 
host operation when the USB is configured.

The Device detection is managed by the software using the Line State field in the Host Status (STATUS.LINESTATE) 
register. The device connection is detected by the host controller when DP or DM is pulled high, depending of the speed 
of the device.

The device disconnection is detected by the host controller when both DP and DM are pulled down using the 
STATUS.LINESTATE registers.

The Device Connection Interrupt bit in INTFLAG (INTFLAG.DCONN) is set if a device connection is detected.

The Device Disconnection Interrupt bit in INTFLAG (INTFLAG.DDISC) is set if a device disconnection is detected.

In host mode, the term pipe is used instead of endpoint. A host pipe corresponds to a device endpoint, refer to "Universal 
Serial Bus Specification revision 2.1." for more information.

The USB sends a USB reset signal when the user writes a one to the USB Reset bit in CTRLB (CTRLB.BUSRESET). 
When the USB reset has been sent, the USB Reset Sent Interrupt bit in the INTFLAG (INTFLAG.RST) is set and all 
pipes will be disabled.

If the bus was previously in a suspended state (Start of Frame Generation Enable bit in CTRLB (CTRLB.SOFE) is zero) 
the USB will switch it to the Resume state, causing the bus to asynchronously set the Host Wakeup Interrupt flag 
(INTFLAG.WAKEUP). The CTRLB.SOFE bit will be set in order to generate SOFs immediately after the USB reset.

During USB reset the following registers are cleared:

z

All Host Pipe Configuration register (PCFG)

z

Host Frame Number register (FNUM)

z

Interval for the Bulk-Out/Ping transaction register (BINTERVAL)

z

Host Start-of-Frame Control register (HSOFC)

z

Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)

z

Pipe Interrupt Flag register (PINTFLAG)

z

Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)

After the reset the user should check the Speed Status field in the Status register (STATUS.SPEED) to find out the 
current speed according to the capability of the peripheral.

Pipe data can be placed anywhere in the RAM. The USB controller accesses these pipes directly through the AHB 
master (built-in DMA) with the help of the pipe descriptors. The base address of the pipe descriptors needs to be written 
in the Descriptor Address register (DESCADD) by the user. Please refer the Pipe Descriptor structure in 

.

Before using a pipe, the user should configure the direction and type of the pipe in Type of Pipe field in the Host Pipe 
Configuration register (PCFG.PTYPE). The pipe descriptor registers should be initialized to known values before using 
the pipe, so that the USB controller does not read the random values from the RAM.