Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
749
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.6.3.12 Alternate Pipe
The user has the possibility to run sequentially several logical pipes on the same physical pipe. It allows addressing of
any device endpoint of any attached device on the bus.
any device endpoint of any attached device on the bus.
Before switching pipe, the user should save the pipe context (Pipe registers and descriptor for pipe n).
After switching pipe, the user should restore the pipe context (Pipe registers and descriptor for pipe n) and in particular
PCFG, and PSTATUS.
PCFG, and PSTATUS.
31.6.3.13 Data Flow Error
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets the Transmit Fail bit in
PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in
PINTENCLR/SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary register
(PINTSMRY) to find out the pipe which triggered the interrupt.Then the user must check the origin of the interrupt’s bank
by looking at the Pipe Bank Status register (STATUS_BK) for each bank. If the Error Flow bit in the STATUS_BK
(STATUS_BK.ERRORFLOW) is set then the user is able to determine the origin of the data flow error. As the user knows
that the endpoint is an IN or OUT the error flow can be deduced as OUT underflow or as an IN overflow.
PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in
PINTENCLR/SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary register
(PINTSMRY) to find out the pipe which triggered the interrupt.Then the user must check the origin of the interrupt’s bank
by looking at the Pipe Bank Status register (STATUS_BK) for each bank. If the Error Flow bit in the STATUS_BK
(STATUS_BK.ERRORFLOW) is set then the user is able to determine the origin of the data flow error. As the user knows
that the endpoint is an IN or OUT the error flow can be deduced as OUT underflow or as an IN overflow.
An underflow can occur during an OUT stage if the host attempts to send data from an empty bank. If a new transaction
is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
An overflow can occur during an IN stage if the device tries to send a packet while the bank is full. Typically this occurs
when a CPU is not fast enough. The packet data is not written to the bank and is lost. If a new transaction is successful,
the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
when a CPU is not fast enough. The packet data is not written to the bank and is lost. If a new transaction is successful,
the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
31.6.3.14 CRC Error
This error exists only for isochronous IN pipes. It sets the PINTFLAG.TRFAIL, which triggers an interrupt if
PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which triggered the interrupt.
Then the user must check the origin of the interrupt’s bank by looking at the bank descriptor STATUS_BK for each bank
and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is set then the user is able to determine the origin of
the CRC error. A CRC error can occur during the IN stage if the USB detects a corrupted packet. The IN packet will
remain stored in the bank and PINTFLAG.TRCPT0/1 will be set.
PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which triggered the interrupt.
Then the user must check the origin of the interrupt’s bank by looking at the bank descriptor STATUS_BK for each bank
and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is set then the user is able to determine the origin of
the CRC error. A CRC error can occur during the IN stage if the USB detects a corrupted packet. The IN packet will
remain stored in the bank and PINTFLAG.TRCPT0/1 will be set.
31.6.3.15 PERR Error
This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if PINTFLAG.PERR is set.
The user must check the PINTSMRY register to find out the pipe which can cause an interrupt.
The user must check the PINTSMRY register to find out the pipe which can cause an interrupt.
A PERR error occurs if one of the error field in the STATUS_PIPE register in the Host pipe descriptor is set and the Error
Count field in STATUS_PIPE (STATUS_PIPE.ERCNT) exceeds the maximum allowed number of Pipe error(s) as
defined in Pipe Error Max Number field in CTRL_PIPE (CTRL_PIPE.PERMAX). Refer to section
Count field in STATUS_PIPE (STATUS_PIPE.ERCNT) exceeds the maximum allowed number of Pipe error(s) as
defined in Pipe Error Max Number field in CTRL_PIPE (CTRL_PIPE.PERMAX). Refer to section
.
If one of the error field in the STATUS_PIPE register from the Host Pipe Descriptor is set and the STATUS_PIPE.ERCNT
is less than the CTRL_PIPE.PERMAX, the STATUS_PIPE.ERCNT is incremented.
is less than the CTRL_PIPE.PERMAX, the STATUS_PIPE.ERCNT is incremented.
31.6.3.16 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
An EXTENDED LPM transaction can be transmitted by any enabled pipe. The PCFGn.PTYPE should be set to
EXTENDED. Other fields as PCFG.PTOKEN, PCFG.BK PCKSIZE.SIZE are irrelevant in this configuration. The user
should also set the EXTREG.VARIABLE in the descriptor as described in
EXTENDED. Other fields as PCFG.PTOKEN, PCFG.BK PCKSIZE.SIZE are irrelevant in this configuration. The user
should also set the EXTREG.VARIABLE in the descriptor as described in
.
When the pipe is configured and enabled, an EXTENDED TOKEN followed by a LPM TOKEN are transmitted. The
device responds with a valid HANDSHAKE, corrupted HANDSHAKE or no HANDSHAKE (TIME-OUT).
device responds with a valid HANDSHAKE, corrupted HANDSHAKE or no HANDSHAKE (TIME-OUT).
If the valid HANDSHAKE is an ACK, the host will immediately proceed to L1 SLEEP and the PINTFLAG.TRCT0 is set.
The minimum duration of the L1 SLEEP state will be the TL1RetryAndResidency as defined in the reference document
"ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". When entering the L1 SLEEP state,
the CTRLB.SOFE is cleared, avoiding Start-of-Frame generation.
The minimum duration of the L1 SLEEP state will be the TL1RetryAndResidency as defined in the reference document
"ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". When entering the L1 SLEEP state,
the CTRLB.SOFE is cleared, avoiding Start-of-Frame generation.
If the valid HANDSHAKE is a NYET PINTFLAG.TRFAIL is set.
If the valid HANDSHAKE is a STALL the PINTFLAG.STALL is set.