Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
761
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.1 Common Device Host Registers
31.8.1.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x0000
Property:
Write-Protected, Write-Synchronised
z
Bit 7– MODE: Operating Mode
This bit defines the operating mode of the USB.
0: USB Device mode
1: USB Host mode
This bit defines the operating mode of the USB.
0: USB Device mode
1: USB Host mode
z
Bits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – RUNSDTBY: Run in Standby Mode
0: USB clock is stopped in standby mode.
1: USB clock is running in standby mode
This bit is Enable-Protected.
0: USB clock is stopped in standby mode.
1: USB clock is running in standby mode
This bit is Enable-Protected.
z
Bit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Synchronization status enable bit in the syn-
chronization register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation
is complete.
This bit is Write-Synchronized
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Synchronization status enable bit in the syn-
chronization register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation
is complete.
This bit is Write-Synchronized
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the USB, to their initial state, and the USB will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is Write-Synchronized.
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the USB, to their initial state, and the USB will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is Write-Synchronized.
Bit
7
6
5
4
3
2
1
0
MODE
RUNSTBY
ENABLE
SWRST
Access
R/W
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0