Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
78
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
13.
Clock System
This chapter only aims to summarize the clock distribution and terminology in the SAM D21 device. It will not explain
every detail of its configuration. For in-depth documentation, see the referenced module chapters.
every detail of its configuration. For in-depth documentation, see the referenced module chapters.
13.1 Clock Distribution
Figure 13-1. Clock distribution
The clock system on the SAM D21 consists of:
z
Clock sources, controlled by SYSCTRL
z
A Clock source is the base clock signal used in the system. Example clock sources are the internal 8MHz
oscillator (OSC8M), External crystal oscillator (XOSC) and the Digital frequency locked loop (DFLL48M).
oscillator (OSC8M), External crystal oscillator (XOSC) and the Digital frequency locked loop (DFLL48M).
z
Generic Clock Controller (GCLK) which controls the clock distribution system, made up of:
z
Generic Clock generators: A programmable prescaler, that can use any of the system clock sources as its
source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the clock feeding the Power
Manager used to generate synchronous clocks.
source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the clock feeding the Power
Manager used to generate synchronous clocks.
z
Generic Clocks: Typically the clock input of a peripheral on the system. The generic clocks, through the
Generic Clock Multiplexer, can use any of the Generic Clock generators as its clock source. Multiple
instances of a peripheral will typically have a separate generic clock for each instance. The DFLL48M clock
input (when multiplying another clock source) is generic clock 0.
Generic Clock Multiplexer, can use any of the Generic Clock generators as its clock source. Multiple
instances of a peripheral will typically have a separate generic clock for each instance. The DFLL48M clock
input (when multiplying another clock source) is generic clock 0.
z
Power Manager (PM)
z
The PM controls synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as well
as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn
on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks.
as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn
on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks.
shows an example where SERCOM0 is clocked by the DFLL48M in open loop mode. The DFLL48M is
enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source, and the generic clock 20, also called
GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source. The SERCOM0 interface,
clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the PM.
GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source. The SERCOM0 interface,
clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the PM.
GCLK Generator 0
SYSCTRL
GCLK
GCLK Generator 1
GCLK Generator x
GCLK Multiplexer 0
(DFLL48M Reference)
(DFLL48M Reference)
GCLK Multiplexer 1
GCLK Multiplexer y
Peripheral z
Peripheral 0
Synchronous Clock
Controller
PM
AHB/APB System Clocks
GCLK_MAIN
_
N
OSC8M
OSC32K
OSCULP32K
XOSC32K
DFLL48M
XOSC
Generic
Clocks
Clocks
FDPLL96M