Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
797
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.5 Host Registers - Common
31.8.5.1 Control B
Name:
CTRLB
Offset:
0x08
Reset:
0x0000
Property:
Write-Protected
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 11 – L1RESUME: Send USB L1 Resume
Writing 0 to this bit has no effect.
1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame generation
is enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the EXTREG.VARIABLE[7:4] bits
field also known as BESL (See LPM ECN).See also
Writing 0 to this bit has no effect.
1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame generation
is enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the EXTREG.VARIABLE[7:4] bits
field also known as BESL (See LPM ECN).See also
.
This bit is cleared when the USB L1 Resume has been sent or when a USB reset is requested.
z
Bit 10 – VBUSOK: VBUS is OK
0: The USB module is notified that the VBUS on the USB line is not powered.
1: The USB module is notified that the VBUS on the USB line is powered.
This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the USB HOST
is configured and enabled, HOST operation is halted. Setting this bit will allow HOST operation when the USB is
configured and enabled.
0: The USB module is notified that the VBUS on the USB line is not powered.
1: The USB module is notified that the VBUS on the USB line is powered.
This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the USB HOST
is configured and enabled, HOST operation is halted. Setting this bit will allow HOST operation when the USB is
configured and enabled.
z
Bit 9 – BUSRESET: Send USB Reset
0: Reset generation is disabled. It is written to zero when the USB reset is completed or when a device disconnec-
tion is detected. Writing zero has no effect.
1: Generates a USB Reset on the USB bus.
0: Reset generation is disabled. It is written to zero when the USB reset is completed or when a device disconnec-
tion is detected. Writing zero has no effect.
1: Generates a USB Reset on the USB bus.
z
Bit 8 – SOFE: Start-of-Frame Generation Enable
0: The SOF generation is disabled and the USB bus is in suspend state.
1: Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is automatically set at
the end of a USB reset (INTFLAG.RST) or at the end of a downstream resume (INTFLAG.DNRSM) or at the end
of L1 resume.
0: The SOF generation is disabled and the USB bus is in suspend state.
1: Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is automatically set at
the end of a USB reset (INTFLAG.RST) or at the end of a downstream resume (INTFLAG.DNRSM) or at the end
of L1 resume.
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit
15
14
13
12
11
10
9
8
L1RESUME
VBUSOK
BUSRESET
SOFE
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SPDCONF[1:0]
RESUME
Access
R
R
R
R
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
0
0