Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

Reading a read-synchronized core register will cause the peripheral bus to stall immediately until the read-
synchronization is complete. STATUS.SYNCBUSY will not be set. Refer to 

 for 

details on the synchronization delay. Note that reading a read-synchronized core register while STATUS.SYNCBUSY is 
one will cause the peripheral bus to stall twice; first because of the ongoing synchronization, and then again because 
reading a read-synchronized core register will cause the peripheral bus to stall immediately.

The user can either poll STATUS.SYNCBUSY or use the Synchronisation Ready interrupt (if available) to check when 
the synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next 
operation will be started once the previous write/read operation is synchronized and/or complete. 

The read request functionality is only available to peripherals that have the Read Request register (READREQ) 
implemented. Refer to the register description of individual peripheral chapters for details.

To avoid forcing the peripheral bus to stall when reading read-synchronized core registers, the read request mechanism 
can be used. 

Writing a one to the Read Request bit in the Read Request register (READREQ.RREQ) will request read-
synchronization of the register specified in the Address bits in READREQ (READREQ.ADDR) and set 
STATUS.SYNCBUSY. When read-synchronization is complete, STATUS.SYNCBUSY is cleared. The read-
synchronized value is then available for reading without delay until READREQ.RREQ is written to one again.

The address to use is the offset to the peripheral's base address of the register that should be synchronized.

Writing a one to the Read Continuously bit in READREQ (READREQ.RCONT) will force continuous read-
synchronization of the register specified in READREQ.ADDR. The latest value is always available for reading without 
stalling the bus, as the synchronization mechanism is continuously synchronizing the given value. 

SYNCBUSY is set for the first synchronization, but not for the subsequent synchronizations. If another synchronization is 
attempted, i.e. by executing a write-operation of a write-synchronized register, the read request will be stopped, and will 
have to be manually restarted.

Note that continuous read-synchronization is paused in sleep modes where the generic clock is not running. This means 
that a new read request is required if the value is needed immediately after exiting sleep. 

Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set 
STATUS.SYNCBUSY. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation 
Ready interrupt (if available) cannot be used for Enable write-synchronization. 

When the enable write-synchronization is ongoing (STATUS.SYNCBUSY is one), attempt to do any of the following will 
cause the peripheral bus to stall until the enable synchronization is complete: 

z

Writing a core register

z

Writing an APB register

z

Reading a read-synchronized core register

APB registers can be read while the enable write-synchronization is ongoing without causing the peripheral bus to stall. 

Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set 
STATUS.SYNCBUSY. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and