Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
819
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.6.7 Host Pipe Interrupt Enable Register
Name:
PINTENCLR
Offset:
0x108 + (n x 0x20)
Reset:
0x0000
Property:
Write-Protected
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register.
This register is cleared by USB reset or when PEN[n] is zero.
register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register.
This register is cleared by USB reset or when PEN[n] is zero.
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 5 – STALL: Received Stall Interrupt Enable
0: The received Stall interrupt is disabled.
1: The received Stall interrupt is enabled and an interrupt request will be generated when the received Stall inter-
rupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding interrupt
request.
0: The received Stall interrupt is disabled.
1: The received Stall interrupt is enabled and an interrupt request will be generated when the received Stall inter-
rupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 4 – TXSTP: Transmitted Setup Interrupt Enable
0: The Transmitted Setup interrupt is disabled.
1: The Transmitted Setup interrupt is enabled and an interrupt request will be generated when the Transmitted
Setup interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding interrupt
request.
0: The Transmitted Setup interrupt is disabled.
1: The Transmitted Setup interrupt is enabled and an interrupt request will be generated when the Transmitted
Setup interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 3 – PERR: Pipe Error Interrupt Enable
0: The Pipe Error interrupt is disabled.
1: The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe Error interrupt Flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding interrupt
request.
0: The Pipe Error interrupt is disabled.
1: The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe Error interrupt Flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 2 – TRFAIL: Transfer Fail Interrupt Enable
0: The Transfer Fail interrupt is disabled.
1: The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt
request.
0: The Transfer Fail interrupt is disabled.
1: The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt
request.
Bit
7
6
5
4
3
2
1
0
STALL
TXSTP
PERR
TRFAIL
TRCPT1
TRCPT0
Access
R
R
RW1
RW1
RW1
RW1
RW1
RW1
Reset
0
0
0
0
0
0
0
0