Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
828
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.7.5 Host Status Bank
Name:
STATUS_BK
Offset:
0x0A & 0x1A
Reset:
0xxxxxxxx
Property:
NA
z
Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – ERROFLOW: Error Flow Status
This bit defines the Error Flow Status.
0: No Error Flow detected.
1: A Error Flow has been detected.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For
Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition
has occurred.
This bit defines the Error Flow Status.
0: No Error Flow detected.
1: A Error Flow has been detected.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For
Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition
has occurred.
z
Bit 0 – CRCERR: CRC Error
This bit defines the CRC Error Status.
0: No CRC Error.
1: CRC Error detected.
This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.
This bit defines the CRC Error Status.
0: No CRC Error.
1: CRC Error detected.
This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.
Bit
7
6
5
4
3
2
1
0
+0
ERROFLOW
CRCERR
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
X
X
X
X
X
X
X
X