Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
848
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
32.8.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00
Property:
Write-Protected
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – RUNSTDBY: Run in Standby
This bit indicates whether the ADC will continue running in standby sleep mode or not:
0: The ADC is halted during standby sleep mode.
1: The ADC continues normal operation during standby sleep mode.
This bit indicates whether the ADC will continue running in standby sleep mode or not:
0: The ADC is halted during standby sleep mode.
1: The ADC continues normal operation during standby sleep mode.
z
Bit 1 – ENABLE: Enable
0: The ADC is disabled.
1: The ADC is enabled.
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
0: The ADC is disabled.
1: The ADC is enabled.
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and STATUS.SYNCBUSY will both be cleared when the reset is complete.
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and STATUS.SYNCBUSY will both be cleared when the reset is complete.
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
ENABLE
SWRST
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0