Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
883
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
33.7.5 Synchronization
Due to the asynchronicity between CLK_MODULE_APB and GCLK_MODULE, some registers must be synchronized
when accessed. A register can require:
when accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z
Software Reset bit in Control A register (CTRLA.SWRST)
z
Enable bit in Control A register (CTRLA.ENABLE)
z
Enable bit in Comparator Control register (COMPCTRLn.ENABLE)
The following register need synchronization when written:
z
Window Control register (WINCTRL)
Refer to the Synchronization chapter for further details.