Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

Product codes
ATSAMD21-XPRO
Page of 1018
888
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
33.9.3 Event Control
Name:
EVCTRL
Offset:
0x02
Reset:
0x0000
Property:
Write-Protected
z
Bits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bits 9:8 – COMPEIx [x=1..0]: Comparator x Event Input
Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, 
the enabled action will be taken for any of the incoming events. There is no way to tell which of the incoming 
events caused the action.
These bits indicate whether a comparison will start or not on any incoming event.
0: Comparison will not start on any incoming event.
1: Comparison will start on any incoming event.
z
Bits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bit 4 – WINEO: Window x Event Output Enable
These bits indicate whether the window x function can generate a peripheral event or not.
0: Window x Event is disabled.
1: Window x Event is enabled.
z
Bits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bits 1:0 – COMPEOx [x=1..0]: Comparator x Event Output Enable
These bits indicate whether the comparator x output can generate a peripheral event or not.
0: COMPx event generation is disabled.
1: COMPx event generation is enabled.
Bit
15
14
13
12
11
10
9
8
COMPEI1
COMPEI0
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WINEO0
COMPEO1
COMPEO0
Access
R
R
R
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0