Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
994
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
3 - While the internal startup is not completed, PA07 pin is driven low by the
chip. Then as all the other pins it is configured as an High Impedance pin.
Errata reference: 12118
chip. Then as all the other pins it is configured as an High Impedance pin.
Errata reference: 12118
Fix/Workaround:
None
4 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
5 - Digital pin outputs from Timer/Counters, AC (Analog Comparator), GCLK
(Generic Clock Controller), and SERCOM (I2C and SPI) do not change value
during standby sleep mode. Errata reference: 12537
(Generic Clock Controller), and SERCOM (I2C and SPI) do not change value
during standby sleep mode. Errata reference: 12537
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep mode
in order to keep digital pin output enabled. This is done by setting the RUNSTDBY
bit in the VREG register.
in order to keep digital pin output enabled. This is done by setting the RUNSTDBY
bit in the VREG register.
6 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
failure.
39.2.2 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost.
Errata reference: 12196
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
39.2.3 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround: