Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
113
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
Figure 16-1.
16-bit Timer/Counter Block Diagram
Note:
1. Refer to
,
for Timer/Counter1 pin
placement and description.
16.2.1 Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures
are described in the section
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures
are described in the section
. The Timer/Counter Control Registers
(TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req.
in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually
masked with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.
in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually
masked with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin.
The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or
decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock
Select logic is referred to as the timer clock (clk
The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or
decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock
Select logic is referred to as the timer clock (clk
T
1
).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all
time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable
frequency output on the Output Compare pin (OC1A/B). See
time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable
frequency output on the Output Compare pin (OC1A/B). See
. The
compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an
Output Compare interrupt request.
Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on
either the Input Capture pin (ICP1) or on the Analog Comparator pins (See
either the Input Capture pin (ICP1) or on the Analog Comparator pins (See
Clock Select
Timer/Counter
D
ATA
B
U
S
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
=
0
TOP
BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
(Int.Req.)
OCnA
(Int.Req.)
(Int.Req.)
OCnB
(Int.Req.)
(Int.Req.)
ICFn (Int.Req.)
TCCRnA
TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn