Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

The Input Capture unit is illustrated by the block diagram shown in 

. The elements of the block 

diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit 
names indicates the Timer/Counter number.

When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog 
Comparator output

 (ACO), and this change confirms to the setting of the edge detector, a capture will be 

triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture 
Register

 (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied 

into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The 
ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by 
software by writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and 
then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary 
register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register.

The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register 
for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be 
set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte 
must be written to the ICR1H I/O location before the low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to 

The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can 
alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog 
Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the 
Analog Comparator Control and Status Register

 (ACSR). Be aware that changing trigger source can trigger a 

capture. The Input Capture Flag must therefore be cleared after the change.

Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same 
technique as for the T1 pin (

). The edge detector is also identical. However, when the 

noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by 

ICFn (Int.Req.)

Analog

Comparator

WRITE

ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

Edge

Detector

TEMP (8-bit)

DATA BUS 

(8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit)

TCNTnL (8-bit)