Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

must be set as output before the OC1x value is visible on the pin. The port override function is generally 
independent of the Waveform Generation mode, but there are some exceptions. Refer to 

 and 

 for details.

The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. 
Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See 

The COM1x1:0 bits have no effect on the Input Capture unit.

The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, 
setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed 
on the next compare match. For compare output actions in the non-PWM modes refer to 

. For fast PWM mode refer to 

, and for phase correct and phase and frequency 

correct PWM refer to 

A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For 
non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits.

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the 
combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The 
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. 
The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-
inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or 
toggle at a compare match (See 

For detailed timing information refer to 

The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is 
always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its 
maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the 
Timer/Counter Overflow Flag

 (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The 

TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with 
the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by 
software. There are no special cases to consider in the Normal mode, a new counter value can be written 
anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between 
the external events must not exceed the resolution of the counter. If the interval between events are too long, 
the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to 
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to 
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) 
matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top 
value for the counter, hence also its resolution. This mode allows greater control of the compare match output 
frequency. It also simplifies the operation of counting external events.