Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
149
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by
setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7.
(See
COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by
setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7.
(See
). The actual OC2x value will only be visible on the port pin if the data direction for
the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the
compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock
cycle the counter is cleared (changes from TOP to BOTTOM).
compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock
cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output
in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on
the polarity of the output set by the COM2A1:0 bits.)
in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on
the polarity of the output set by the COM2A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to
toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum
frequency of f
toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum
frequency of f
oc2
= f
clk_I/O
/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode,
except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
18.7.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform
generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts
repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3,
and OCR2A when MGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared
on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while
downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower
maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-
slope PWM modes, these modes are preferred for motor control applications.
generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts
repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3,
and OCR2A when MGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared
on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while
downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower
maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-
slope PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the
counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on
counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on
. The TCNT2 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-
inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2x and TCNT2.
inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2x and TCNT2.
f
OCnxPWM
f
clk_I/O
N 256
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=