Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
158
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
pin is configured as an output. This feature allows software control of the counting.
18.11.3 TCNT2 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-
bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock.
Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match
between TCNT2 and the OCR2x Registers.
bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock.
Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match
between TCNT2 and the OCR2x Registers.
18.11.4 OCR2A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on
the OC2A pin.
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on
the OC2A pin.
18.11.5 OCR2B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on
the OC2B pin.
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on
the OC2B pin.
18.11.6 TIMSK2 – Timer/Counter2
Interrupt Mask Register
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2
Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in
Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in
Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
1
0
1
clk
T2S
/128 (From prescaler)
1
1
0
clk
T
2
S
/256 (From prescaler)
1
1
1
clk
T
2
S
/1024 (From prescaler)
Table 18-9.
Clock Select Bit Description
CS22
CS21
CS20
Description
Bit
7
6
5
4
3
2
1
0
TCNT2[7:0]
TCNT2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OCR2A[7:0]
OCR2A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OCR2B[7:0]
OCR2B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
OCIE2B
OCIE2A
TOIE2
TIMSK2
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0