Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

The following sections describe each of these modes. Possible status codes are described along with figures 
detailing data transmission in each of the modes. These figures contain the following abbreviations:

S: START condition

Rs: REPEATED START condition

R: Read bit (high level at SDA)

W: Write bit (low level at SDA)

A: Acknowledge bit (low level at SDA)

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P: STOP condition

SLA: Slave Address

, circles are used to indicate that the TWINT Flag is set. The numbers in the 

circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must 
be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the 
TWINT Flag is cleared by software.

When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate software action. For 
each status code, the required software action and details of the following serial transfer are given in 

. Note that the prescaler bits are masked to zero in these tables.

In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see 

In order to enter a Master mode, a START condition must be transmitted. The format of the following address 
packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is 
transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned 
in this section assume that the prescaler bits are zero or are masked to zero.

A START condition is sent by writing the following value to TWCR:

TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START 
condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the 2-wire Serial 

value

1

X

1

0

X

1

0

X

Device 1

MASTER

TRANSMITTER

Device 2

SLAVE

RECEIVER

Device 3

Device n

SDA

SCL

........

R1

R2

V

CC